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Thread: Interrupt handling

  1. #11
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    May 2008
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    Re: Interrupt handling

    Quote Originally Posted by Resilient View Post
    I was reading through the mega640 data sheet and it looks like there are two kinds of interrupts, some that throw a flag and others that dont.

    I am a little confused as to which is which. It sounds to me like if it is set up to be edge triggered, then it will set a flag when it detects an edge even if it is disabled. Whereas if it is level triggered, then it will only throw an interrupt if it is enabled and the level is held low for at least 5 clock cycles.

    So it sounds like what I want is an edge triggered interrupt so that I can disable it, read the value, enable it and then it can handle the interrupt if the flag was set while reading the value. Can anyone confirm or deny this?

    I read it here:

    Pages: top of 18 and 112
    A little background in the AVR architecture can help explain this some I think. Back in the original days of the AVR, all interrupts acted in the following way: if a condition occured AND the particular interrupt was enabled a flag was set. If interrupts were enabled (the I-bit in the SREG set to 1) then the ISR would be called. When an ISR was entered, the I-bit was disabled, when RETI was called at the end of the ISR, the I-bit was enabled again and the particular flag was cleared. Under this setup, even if an event occurs while handling an interrupt, the flag will be set (note, the issue of a particular event happening twice and the second occurance being missed, may still occur, as you can't set a one-bit flag to represent the number of times an event occured).

    But there was a problem here. Most mid-size (28 and 40 pin) AVRs had several interrupts related to each counter or serial device, but they typically only had 2-3 external interrupts. Then along came the PIN CHANGE INTERRUPTS. These interrupts are slightly limited compared to the external interrupts we had/have. They of course route all the pins on a particular port to a shared interrupt vector, you can only interrupt on pin-change (unlike external interrupts, which can be set to RISING, FALLING, or LOW level).

    All of the above interrupts (external, pin-change, counter, serial) use flags. There are a couple warnings in there, that pin-change and rising/falling external interrupts are asynchronously generated, but that a low-level external interrupt is not (so you can't reliably detect a low-pulse shorter than the AVR clock-cycle, but you can detect the high-to-low transition...).

    I'm really not sure where these "flagless" interrupts exist.... however, I think it is safe to say: you probably won't be using them right now.

    If I am correct, you are using interrupts to read quadrature encoders? In such a case, I recommend using the INTx hardware external interrupts, with either a rising or falling configuration. Note that if you use the pin-change interrupts, you end up doubling the number of incoming pulses, but typically it makes the quadrature decoding more tedious, which can cause an ISR to become too long (especially if you have more than 1 channel on a particular pin-change vector active as an interrupt, and have to start reading pins and crud like that....)


  2. Re: Interrupt handling

    Thanks Fergs,
    I am using it for quadrature encoders and I will set it up with external hardware interrupts. But I will be doing some stuff with timers soon and know there are going to be some bugs to deal with there so I am trying to learn all I can before it gets too complex.


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